As shown in FIG. 1, a typical class-D amplifier 10 includes a control circuit 12 and an output stage 14 operated by the control circuit 12. According to an audio input signal AudioIN, the control circuit 12 provides pulse width modulation (PWM) output signals VOUTP and VOUTN to switch PMOS transistors P1, P2 and NMOS transistors N1, N2 in the output stage 14 for driving a load. In order to prevent the output signals VOUTP and VOUTN from having excessively short PWM pulses to cause the output stage 14 to short through, a minimum pulse mechanism is provided to enforce the PWM pulses of the output signals VOUTP and VOUTN to have pulse widths not shorter than a minimum pulse width.
There are two conventional methods for minimum pulse generation in a class-D amplifier; one is to generate a one shot pulse by use of a timing delay difference between two input channels, for example, disclosed by U.S. Pat. No. 6,262,632 to Corsi et al., and the other is to generate a minimum pulse by use of rising edge and falling edge detection of a variable switching pulse, for example, proposed by U.S. Pat. No. 6,847,257 to Edwards et al. However, even with either one of these two methods, when the audio input signal AudioIN has an amplitude over than the internal switching amplitude, the PWM output would be missed and then cause the output stage 14 to continue short through. Moreover, the minimum pulse also introduces a nonlinear phenomenon.